Shang Liu

Shang Liu

PhD candidate at HKUST

About me

I am Shang Liu, a second-year PhD student at the Electronic and Computer Engineering Department of the Hong Kong University of Science and Technology (HKUST) advised by Prof. Zhiyao Xie. Before that, I received a bachelor’s degree in EE from Beihang University in 2023. My research interests include the large language model, AI algorithms, and electronic design automation.

Research Interests

  • Large Language Model
  • AI Algorithm
  • Electronic Design Automation

Education

  • Ph.D. Electronic and Computer Engineering, the Hong Kong University of Science and Technology, Aug. 2023 - Now
  • B.Eng. Electrical Engineering, Beihang University, Sep. 2019 - Jul. 2023

Publication

  • Shang Liu* Jing WANG*, Wenji Fang, and Zhiyao Xie, “SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits”, ACM/IEEE Design Automation Conference (DAC), 2025.

  • Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, and Zhiyao Xie, “NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph”, ACM/IEEE Design Automation Conference (DAC), 2025.

  • Wenji Fang, Shang Liu, Jing Wang, and Zhiyao Xie, “CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design”, International Conference on Learning Representations (ICLR), 2025.

  • Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, and Zhiyao Xie, “RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

  • Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, and Zhiyao Xie, “Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

  • Wenji Fang, Shang Liu, Hongce Zhang, and Zhiyao Xie, “A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

  • Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, and Hongce Zhang, “AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.

  • Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, and Zhiyao Xie, “Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

  • Shang Liu*, Yao Lu*, Wenji Fang*, Mengming Li, and Zhiyao Xie, “OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)”, International Conference on Computer-Aided Design (ICCAD), 2024.

  • Shang Liu, Wenji Fang, et al., “Rtlcoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution”, IEEE International Workshop on LLM-Aided Design (LAD) 2024. Best Paper Nomination.

  • Yao Lu*, Shang Liu*, et al., “RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model”, Asia and South Pacific Design Automation Conference (ASP-DAC) 2024.

  • Wenji Fang, Shang Liu, et al., “Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization”, ACM/IEEE Design Automation Conference (DAC) 2024.

  • Wenji Fang, Yao Lu, Shang Liu, et al., “MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design”, IEEE/ACM International Conference on Computer Aided Design (ICCAD) 2023.